In general, memory management systems translate the logical addresses of executive and user programs into physical addresses available in the system memory address space. This facility allows more flexible utilization of physical memory through the logical concatenation of non-contiguous memory areas to accomodate the requirements of specific programs. In addition, the logical address space of the processor can be effectively multiplied with each defined mapping, allowing utilization of a much greater physical address space than would otherwise be available. Such memory management systems often provide protection against unauthorized access, such as preventing user programs from accessing executive-reserved memory, and write protection to preclude inadvertant writing to read-only reserved memory.
In some of these prior art memory management systems, the logical-to-physical address translation is performed using one or more arithmetic operations, and thus requires significant dedicated hardware. Other known memory management systems employ special latches to index into a dedicated memory area to retrieve mapping data. Some of the latter type utilize cache type memories and include multiple comparators to detect successful mappings. Most such implementations are undesirable or impractical for integration due to excessive hardware requirements, limited mapping capabilities, or relatively slow response speed.